This invention relates to a priority encoder which is usable in a floating point processor or the like.
In a conventional priority encoder, when implementing a multi-input priority encoder in a semiconductor integrated circuit, a plurality of 4-bit or 8-bit priority encoders are used, and individual outputs (encode output and carry output) are connected to logic gates as inputs, so that the circuit composition is complicated. In the case of zero detection, for example, the carry signal generated by a 4-bit or 8-bit priority encoder progagates through each 4-bit or 8-bit priority encoder, and is thus most time-consuming, making it difficult to increase the operation speed.